S2MM_CONTROL (S2MM Control) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This value provides control for S2MM transfers from stream to memory map.

Figure 1. S2MM_CONTROL

Table 1. S2MM_CONTROL Details
Bits Field Name Description
31 to 28 Reserved These bits are reserved and should be set to zero.
27 RXSOF Start of Frame. Flag indicating the first buffer to be processed. This flag is set by the sw/user to indicate to AXI DMA that this descriptor describes the start of the packet. The buffer associated with this descriptor is received first.
  • 0 = Not Start of Frame.
  • 1 = Start of Frame.

This is applicable only when AXI_DMA is configured in Micro mode.

26 Receive End Of Frame End of Frame. Flag indicating the last buffer to be processed. This flag is set by the sw/user to indicate to AXI DMA that this descriptor describes the end of the packet. The buffer associated with this descriptor is received last.
  • 0 = Not End of Frame.
  • 1 = End of Frame.

This is applicable only when AXI_DMA is configured in Micro mode.

25 to 0 Buffer Length This value indicates the amount of space in bytes available for receiving data in an S2MM stream. The usable width of buffer length is specified by the parameter, Width of Buffer Length Register. A maximum of 67,108,863 bytes of transfer can be described by this field.
Note: The total buffer space in the S2MM descriptor chain (that is, the sum of buffer length values for each descriptor in a chain) must be, at a minimum, capable of holding the maximum receive packet size. Undefined results occur if a packet larger than the defined buffer space is received.
Note: Setting the Buffer Length Register Width smaller than 26 reduces FPGA resource utilization.
Note: When configuring the AXI_DMA in Micro mode, this value should not exceed the following equation:

(S2MM Memory Mapped Datawidth/8)*Burst_length - 1