The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter/Value | User Parameter/Value | Default Value |
|---|---|---|
| Enable Scatter Gather Engine | c_include_sg | 1 |
| Enable Multi Channel Support | c_enable_multi_channel | 0 |
| Number of Channels (MM2S) | c_num_mm2s_channels | 1 |
| Number of Channels (S2MM) | c_num_s2mm_channels | 1 |
| Width of Buffer Length Register | c_sg_length_width | 14 |
| Enable Asynchronous clocks | c_prmry_is_aclk_async | 0 |
| Enable Control/Status Stream | c_sg_include_stscntrl_strm | 1 |
| Enable Micro DMA | c_micro_dma | 0 |
| Enable Read Channel | c_include_mm2s | 1 |
| Memory Map Data Width (MM2S) | c_m_axi_mm2s_data_width | 32 |
| Stream Data Width (MM2S) | c_m_axis_mm2s_tdata_width | 32 |
| Allow Unaligned Transfers (MM2S) | c_include_mm2s_dre | 0 |
| Max Burst Size (MM2S) | c_mm2s_burst_size | 16 |
| Enable Write Channel | c_include_s2mm | 1 |
| Use Rxlength in Status Stream | c_sg_use_stsapp_length | 0 |
| Memory Map Data Width (S2MM) | c_m_axi_s2mm_data_width | 32 |
| Stream Data Width (S2MM) | c_s_axis_s2mm_tdata_width | 32 |
| Allow Unaligned Transfers (S2MM) | c_include_s2mm_dre | 0 |
| Max Burst Size (S2MM) | c_s2mm_burst_size | 16 |
| Address Width (32-64) | c_addr_width | 32 |