Port Descriptions - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

The AXI DMA I/O signals are described in the following table.

Table 1. I/O Signal Descriptions
Signal Name Interface Signal Type Init Status Description
s_axi_lite_aclk Clock I AXI4-Lite Clock.
m_axi_sg_aclk Clock I AXI DMA Scatter Gather Clock
m_axi_mm2s_aclk Clock I AXI DMA MM2S Primary Clock
m_axi_s2mm_aclk Clock I AXI DMA S2MM Primary Clock
axi_resetn Reset I AXI DMA Reset. Active-Low reset. When asserted Low, resets entire AXI DMA core. Must be synchronous to s_axi_lite_aclk.
mm2s_introut Interrupt O 0 Interrupt Out for Memory Map to Stream Channel.
s2mm_introut Interrupt O 0 Interrupt Out for Stream to Memory Map Channel.
axi_dma_tstvec NA O 0 Debug signals for internal use.
AXI4-Lite Interface Signals
s_axi_lite_* S_AXI_LITE I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
MM2S Memory Map Read Interface Signals
m_axi_mm2s_* M_AXI_MM2S I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
MM2S Master Stream Interface Signals
mm2s_prmry_reset_out_n M_AXIS_MM2S O 1 Primary MM2S Reset Out. Active-Low reset.
m_axis_mm2s_* M_AXIS_MM2S I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
MM2S Master Control Stream Interface Signals
mm2s_cntrl_reset_out_n M_AXIS_CNTRL O 1 Control Reset Out. Active-Low reset.
m_axis_mm2s_cntrl_* M_AXIS_CNTRL I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
S2MM Memory Map Write Interface Signals
m_axi_s2mm_* M_AXI_S2MM I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
S2MM Slave Stream Interface Signals
s2mm_prmry_reset_out_n S_AXIS_S2MM O 1 Primary S2MM Reset Out. Active-Low reset.
s_axis_s2mm_* S_AXIS_S2MM I Input/ Output See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
Scatter Gather Memory Map Read Interface Signals
m_axi_sg_* M_AXI_SG I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.
Scatter Gather Memory Map Write Interface Signals
m_axi_sg* M_AXI_SG I/O See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for the AXI4 signal.