Writes start at the Buffer Address and consist of VSIZE write bursts, each having HSIZE
bytes. The starting address of each write burst is a STRIDE address greater than the
starting address of the previous burst write. On the AXI4-Stream
interface, this is received on the s_axis_s2mm_interface as one
contiguous packet and is terminated with a single assertion of tlast on
the last data beat of the transfer. The size of the arriving packet should match with
what is programmed in Buffer Descriptors.