Memory Map Data Width - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

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7.1 English

Data width in bits of the AXI S2MM Memory Map Write data bus. Valid values are 32, 64, 128, 256, 512 and, 1,024.

TIP: In the Vivado IP integrator, this parameter is automatically set based on the data width of the Streaming Interface. Update this parameter by changing the switch to 'Manual'.