MM2S_DMASR (MM2S DMA Status Register – Offset 04h) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)
Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This register provides the status for the Memory Map to Stream DMA Channel.

Figure 1. MM2S DMASR Register

Table 1. MM2S_DMASR Register Details
Bits Field Name Default Value Access Type Description
0 Halted 1 RO DMA Channel Halted. Indicates the run/stop state of the DMA channel.
  • 0 = DMA channel running.
  • 1 = DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and Scatter Gather (SG) operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1.
Note: When halted (RS= 0 and Halted = 1), writing to TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
1 Idle 0 RO DMA Channel Idle. Indicates the state of AXI DMA operations. For Scatter/Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations. The IDLE bit is associated with the BDs. The DMA might be in IDLE state, there might be active data on the AXI interface.

For Direct Register Mode when IDLE indicates the current transfer has completed.

  • 0 = Not Idle. For Scatter/Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.
  • 1 = Idle. For Scatter/Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.
Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
2 Reserved 0 RO Writing to this bit has no effect and it is always read as zero.
3 SGIncld C_ INCLUDE_ SG RO
  • 1= Scatter Gather Enabled
  • 0= Scatter Gather not enabled
4 DMAIntErr 0 RO DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No DMA Internal Errors
  • 1 = DMA Internal Error detected. DMA Engine halts.
Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
5 DMASlvErr 0 RO DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No DMA Slave Errors.
  • 1 = DMA Slave Error detected. DMA Engine halts.
6 DMADecErr 0 RO DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No DMA Decode Errors.
  • 1 = DMA Decode Error detected. DMA Engine halts.
7 Reserved 0 RO Writing to this bit has no effect, and it is always read as zeros.
8 SGIntErr 0 RO Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information. This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No SG Internal Errors.
  • 1 = SG Internal Error detected. DMA Engine halts.
Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
9 SGSlvErr 0 RO Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No SG Slave Errors.
  • 1 = SG Slave Error detected. DMA Engine halts.
Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
10 SGDecErr 0 RO Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0 = No SG Decode Errors.
  • 1 = SG Decode Error detected. DMA Engine halts.
Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
11 Reserved 0 RO Writing to this bit has no effect, and it is always read as zeros.
12 IOC_Irq 0 R/WC Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.
  • 0 = No IOC Interrupt.
  • 1 = IOC Interrupt detected.

Writing a 1 to this bit clears it.
13 Dly_Irq 0 R/WC Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer timeout. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.
  • 0 = No Delay Interrupt.
  • 1 = Delay Interrupt detected.1 = IOC Interrupt detected.

Writing a 1 to this bit clears it.

Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
14 Err_Irq 0 R/WC Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.

Writing a 1 to this bit clears it.

  • 0 = No error Interrupt.
  • 1 = Error interrupt detected.
15 Reserved 0 RO Always read as zero.
23 to 16 IRQThresholdSts 01h RO Interrupt Threshold Status. Indicates current interrupt threshold value. The value programmed in the IRQ Threshold field in MM2S_CR is decremented on every packet transfer and reflected here. Before the DMA is started or before sending the first packet, this register will have the same value as programmed in the IRQ Threshold field of MM2S_CR.
Note: Applicable only when Scatter Gather is enabled.
31 to 24 IRQDelaySts 00h RO Interrupt Delay Time Status. Indicates current interrupt delay time value.
Note: Applicable only when Scatter Gather is enabled.