- AXI4 compliant
- Optional Independent Scatter/Gather Direct Memory Access (DMA) support
- Provides offloading of DMA management work from the CPU
- Provides fetch and update of transfer descriptors independent from primary data bus
- Allows descriptor placement to be in any memory-mapped location separate from data buffers. For example, descriptors can be placed in block RAM.
- Provides optional cyclic operation
- Optional Direct Register Mode (no scatter/gather support)
A lower performance but less FPGA-resource-intensive mode can be enabled by excluding the Scatter Gather engine. In this mode transfers are commanded by setting a Source Address (for MM2S) or Destination Address (For S2MM) and then specifying a byte count in a length register.
- Primary AXI4 data width support of 32, 64, 128, 256, 512, and, 1,024 bits
- Primary AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512, and, 1,024 bits
- Optional Data Re-alignment Engine for a stream data width up to 512 bits
Allows data realignment to the byte (8 bits) level on the primary memory map and stream datapaths
- Optional AXI Control and Status Streams to interface to AXI Ethernet IP
Provides optional Control Stream for the MM2S Channel and Status Stream for the S2MM channel to offload low-bandwidth control and status from the high-bandwidth datapath.
- Optional Micro mode
AXI DMA can be configured to deliver a low footprint, low performance IP that can handle the transfer of small packets. Read the following chapters for more information.