MM2S_CONTROL (MM2S Control) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This value provides control for MM2S transfers from memory map to stream.

Figure 1. MM2S_CONTROL

Table 1. MM2S_CONTROL Details
Bits Field Name Description
25 to 0 Buffer Length

Indicates the size in bytes of the transfer buffer. This value indicates the amount of bytes to transmit out on the MM2S stream. The usable width of buffer length is specified by the parameter, Width of Buffer Length Register. A maximum of 67,108,863 bytes of transfer can be described by this field. When configuring the AXI_DMA in Micro mode, this value should not exceed the following equation:

(MM2S Memory Mapped Data width/8)*Burst_length - 1

Note: Setting the buffer length register width smaller than 26 reduces FPGA resource utilization.
26 Transmit End Of Frame

(TXEOF)

End of Frame. Flag indicating the last buffer to be processed. This flag is set by the CPU to indicate to AXI DMA that this descriptor describes the end of the packet. The buffer associated with this descriptor is transmitted last.

  • 0= Not End of Frame.
  • 1= End of Frame.
Note: For proper operation, there must be a Start of Frame (SOF) descriptor (TXSOF=1) and an End of Frame (EOF) descriptor (TXEOF=1) per packet. It is valid to have a single descriptor describe an entire packet that is a descriptor with both TXSOF=1 and TXEOF=1.
27 TXSOF

Start of Frame. Flag indicating the first buffer to be processed. This flag is set by the CPU to indicate to AXI DMA that this descriptor describes the start of the packet. The buffer associated with this descriptor is transmitted first.

  • 0= Not start of frame.
  • 1= Start of frame.
Note: When Status Control Stream is enabled, user application data from APP0 to APP4 of the Start of Frame (SOF) descriptor (TXSOF=1) is transmitted on the control stream output.
31 to 28 Reserved This bit is reserved and should be written as zero.