Revision History - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)
Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

The following table shows the revision history for this document.

Section Revision Summary
06/20/2024 Version 7.1
MM2S_CONTROL (MM2S Control) Updated Burst Length field equation.
MM2S_STATUS (MM2S Status) Updated Transferred Bytes field description.
S2MM_CONTROL (S2MM Control) Updated Buffer Length field description.
Field Descriptions Updated Width of Buffer Length Register description.
04/27/2022 Version 7.1
Performance Updated section.
Scatter Gather Descriptor Updated section.
06/14/2019 Version 7.1
Entire document Updated figures.
MM2S_DMASR (MM2S DMA Status Register – Offset 04h) Updated table.
MM2S_DMASR (MM2S DMA Status Register – Offset 04h) Updated table.
Field Descriptions Added Enable Single AXI4 Data Interface section.
04/04/2018 Version 7.1
N/A Added support for 64 MB data transfer.
10/04/2017 Version 7.1
N/A
  • Added Documentation Navigator and Design Hubs to this appendix.
  • Added Automotive Applications Disclaimer.
  • Updated Data Re-Alignment Engine support to 512 bits (was 64 bits).
10/05/2016 Version 7.1
N/A
  • Added a note about the AXI4-Lite write access register to the beginning of the Register Space section.
  • Updated S2MM description.
11/18/2015 Version 7.1
N/A Added support for UltraScale+ families.
04/01/2015 Version 7.1
N/A
  • Fixed link to master answer record.
  • Added support for 64-bit addressing.
04/02/2014 Version 7.1
N/A
  • Added information about the Air Traffic Generator.
  • Added information about optional Micro DMA.
  • Added axi_dma_tstvec to I/O signals.
12/18/2013 Version 7.1
N/A Added AMD UltraScale™ architecture support.
10/02/2013 Version 7.1
N/A
  • Added example design
  • Added Cyclic BD Enable.
  • Modified Bits 26 and 27 of the S2MM_CONTROL register.
  • Updated screen displays.
  • Added IP integrator information.
  • Added Enable Micro DMA option.
03/20/2013 Version 7.0
N/A
  • Revision number advanced to 7.0 to align with core version number 7.0.
  • Updated for Vivado Design Suite support and core version 7.0
  • Updated Debugging appendix.
  • Removed one screen capture and updated another in Chapter 4.
  • Removed ISE™, CORE Generator™, Virtex™-6, and AMD Spartan™ - 6 material.
  • Removed Design Parameters and AXI DMA System Configuration sections from Chapter 3.
12/18/2012 Version 3.2
N/A
  • Updated for 14.4/2012.4 support and core version 6.03a.
  • Updated Debugging appendix.
  • Updated screen captures in Chapter 4.
  • Replaced Figure 1-1.
  • Updated devices in Table 2-1, System Performance.
  • Updated resource numbers in Tables 2-4, 2-5, and 2-6.
  • Removed Interconnect Parameters and Allowable Parameter Combinations sections.
  • Updated Output Generation sections in Chapters 4 and 7
10/16/2012 Version 3.1
N/A
  • Updated for 14.3/2012.3 support.
  • Document cleanup
07/25/2012 Version 3.0
N/A Added Vivado tools support and AMD Zynq™ 7000 support.
04/24/2012 Version 2.0
N/A
  • Added multichannel support
  • Added 2-D transactions support
  • Added keyhole support
  • Added Cache and User controls for AXI memory side Interface
10/19/2011 Version 1.0
Initial release. N/A