Test Bench for the Example Design - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This section contains information about the provided test bench in the Vivado Design Suite.

The following figure shows the test bench for the AXI DMA example design. The top-level test bench generates a 200 MHz differential clock and drives an initial reset to the example design.

Figure 1. AXI DMA Example Design Test Bench