Test Bench for the Example Design - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

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7.1 English

This section contains information about the provided test bench in the Vivado Design Suite.

Figure 5-2: AXI DMA Example Design Test Bench

X-Ref Target - Figure 5-2


This Figure shows the test bench for the AXI DMA example design. The top-level test bench generates a 200 MHz differential clock and drives an initial reset to the example design.