SG_CTL (Scatter/Gather User and Cache Control Register—Offset 2Ch) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

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7.1 English

This register is available only when DMA is configured in multichannel mode.

Figure 1. SG_CTL Register
AXI DMA pg021_sg_ctl_register_x14601 Sheet.8 31 Sheet.9 Sheet.10 31 31 Sheet.11 24 Sheet.12 Sheet.13 12 12 Sheet.29 0 Sheet.30 Sheet.31 0 0 Sheet.51 Sheet.52 X14601 X14601 Sheet.55 Sheet.56 SG_CACHE SG_CACHE Sheet.14 0 Sheet.15 Sheet.16 4 4 Sheet.17 Sheet.18 Sheet.19 Rsvd Rsvd Sheet.23 0 Sheet.24 Sheet.25 8 8 Sheet.32 Sheet.33 Sheet.34 SG_USER SG_USER Sheet.35 Reserved Reserved Sheet.3 11 11 Sheet.1 Sheet.2 7 7 Sheet.4 3 3
Table 1. SG_CTL Register Details
Bits Field Name Default Value Access Type Description

3 to 0

SG_CACHE 0011b R/W Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.
7 to 4 Reserved 0 RO Writing to these bits has no effect and they are always read as zeros.
11 to 8 SG_USER 0 R/W Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.