S2MM_DA (S2MM DMA Destination Address Register – Offset 48h) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This register provides the Destination Address for writing to system memory for the Stream to Memory Map to DMA transfer.

Figure 1. S2MM_DA Register

Table 1. S2MM_DA Register Details
Bits Field Name Default Value Access Type Description
31 to 0 Destination Address zeros R/W Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.