This register provides the Tail Descriptor Pointer for the Memory Map to Stream DMA Scatter Gather Descriptor Management.
Figure 1. MM2S_TAILDESC Register
| Bits | Field Name | Default Value | Access Type | Description |
|---|---|---|---|---|
| 5 to 0 | Reserved | 0 | RO | Writing to these bits has no effect, and they are always read as zeros. |
| 31 to 6 | Tail Descriptor Pointer | zeros | R/W | Indicates the pause pointer in a descriptor chain. The AXI DMA SG
Engine pauses descriptor fetching after completing operations on the
descriptor whose current descriptor pointer matches the tail
descriptor pointer. When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMASG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point. Note: The
software must not move the tail pointer to a location that has
not been updated. The software processes and reallocates all
completed descriptors (Cmplted = 1), clears the completed bits
and then moves the tail pointer. The software must move the
pointer to the last descriptor it updated. Descriptors must be
16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any
other alignment has undefined results.
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