S2MM_DMACR (S2MM DMA Control Register – Offset 30h) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID: PG021
Release Date: 2024-06-20
Version: 7.1 English

This register provides control for the Stream to Memory Map DMA Channel.

Figure 1. S2MM_DMACR Register

Table 1. S2MM_DMACR Register Details
Bits	Field Name	Default Value	Access	Description
0	RS	0	R/W	Run/Stop control for controlling running and stopping of the DMA channel. 0 = Stop – DMA stops when current (if any) DMA operations are complete. For Scatter/Gather Mode pending commands/ transfers are flushed or completed. AXI4-Streams are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt. For Direct Register Mode pending commands/transfers are flushed or completed. AXI4-Streams are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed. The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations. 1 = Run – Start DMA operations. The halted bit in the DMA Status Register deasserts to 0 when the DMA engine begins operations.
1	Reserved	1	RO	Writing to this bit has no effect, and is always read as 1.
2	Reset	0	R/W	Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed. AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR. Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 = Reset not in progress. Normal operation. 1 = Reset in progress.
3	Keyhole	0	R/W	Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled. This bit is non functional when DMA is used in multichannel mode.
4	Cyclic BD Enable	0	R/W	When set to 1, you can use the DMA in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the 'Completed' bit of the BD. With this feature, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors. This bit is non functional when DMA operates in MultiChannel mode or in Direct Register Mode.
11 to 5	Reserved	0	RO	Writing to these bits has no effect and they are always read as zeros.
12	IOC_IRqEn	0	R/W	Interrupt on Complete Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the "Complete bit" bit set. 0 = IOC Interrupt disabled. 1 = IOC Interrupt enabled.
13	Dly_IrqEn	0	R/W	Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 = Delay Interrupt disabled. 1 = Delay Interrupt enabled. Note: Applicable only when Scatter Gather is enabled.
14	Err_IrqEn	0	R/W	Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 = Error Interrupt disabled. 1 = Error Interrupt enabled.
15	Reserved	0	RO	Writing to this bit has no effect, and it is always read as zeros.
23 to 16	IRQThreshold	01h	R/W	Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: Applicable only when Scatter Gather is enabled.
31 to 24	IRQDelay	00h	R/W	Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout is a mechanism for causing the DMA engine to generate an interrupt after the delay time period has expired. The timer begins counting at the end of a packet and resets with the receipt of a new packet or a timeout event occurs. 1 Timeout Interval =125´ (clock period of SG clock) Setting a value of 3 here results in a delay timeout of 125 x 3 x (clock period of SG clock). Note: Setting this value to zero disables the delay timer interrupt. Note: Applicable only when Scatter Gather is enabled.