S2MM_STATUS (S2MM Status) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This value provides status for S2MM transfers from stream to memory map.

Figure 1. S2MM_STATUS

Table 1. S2MM_STATUS Description
Bits Field Name Description
25 to 0 Transferred Bytes This value indicates the amount of data received and stored in the buffer described by this descriptor. This might or might not match the buffer length. For example, if this descriptor indicates a buffer length of 1,024 bytes but only 50 bytes were received and stored in the buffer, then the Transferred Bytes field indicates 0x32. The entire receive packet length can be determined by adding the Transferred Byte values from each descriptor from the RXSOF descriptor to the Receive End of Frame (RXEOF) descriptor.
Note: The usable width of Transferred Bytes is specified by the parameter, Width of Buffer Length Register. A maximum of 67,108,863 bytes of transfer can be described by this field.
Note: Setting the Buffer Length Register Width smaller than 26 reduces FPGA resource utilization. This field is not updated when AXI_DMA is configured in Micro mode.
26 RXEOF End of Frame. Flag indicating buffer holds the last part of packet. This bit is set by AXI DMA to indicate to the sw/user that the buffer associated with this descriptor contains the end of the packet.
  • 0= Not End of Frame.
  • 1= End of Frame.
Note: User Application data sent through the status stream input is stored in APP0 to APP4 of the RXEOF descriptor when the Control/Status Stream is enabled.
27 RXSOF Start of Frame. Flag indicating buffer holds first part of packet. This bit is set by AXI DMA to indicate to the sw/user that the buffer associated with this descriptor contains the start of the packet.
  • 0= Not start of frame.
  • 1= Start of frame.
28 DMAIntErr DMA Internal Error. Internal Error detected by primary AXI Data Mover. This error can occur if a 0 length bytes to transfer is fed to the AXI Data Mover. This only happens if the Buffer Length specified in the fetched descriptor is set to 0. This error can also be caused if an under-run or over-run condition.

This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.

  • 0= No DMA Internal Errors.
  • 1= DMA Internal Error detected. DMA Engine halts.
29 DMASlvErr DMA Slave Error. Slave Error detected by primary AXI Data Mover. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.
  • 0= No DMA Slave Errors.
  • 1= DMA Slave Error detected. DMA Engine halts.
30 DMADecErr

DMA Decode Error. Decode Error detected by primary AXI Data Mover. This error occurs if the Descriptor Buffer Address points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.

  • 0= No DMA Decode Errors.
  • 1= DMA Decode Error detected. DMA Engine halts.
31 Cmplt Completed. This indicates to the software that the DMA Engine has completed the transfer as described by the associated descriptor. The DMA Engine sets this bit to 1 when the transfer is completed. The software can manipulate any descriptor with the Completed bit set to 1.
  • 0= Descriptor not completed.
  • 1= Descriptor completed.
Note: If a descriptor is fetched with this bit set to 1, the descriptor is considered a stale descriptor. An SGIntErr is flagged and the AXI DMA engine halts.