Example Design - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

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7.1 English

This chapter contains information about the example design provided in the Vivado® Design Suite.

The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown in This Figure . This includes mixed-mode clock manager (MMCME2), register configuration, data generator, and data checker modules.

Figure 5-1: Block Diagram of Example Design

X-Ref Target - Figure 5-1


This example design demonstrates transactions on the AXI4-Lite, AXI4, and AXI4-Stream interfaces of the DUT.

Clock generator : MMCME2 is used to generate the clocks for the example design. When the DUT is in synchronous mode, MMCME2 generates a 100 MHz clock for all the AXI interfaces in the example design. When in asynchronous mode, MMCME2 generates a 50 MHz clock for the AXI4-Lite interface and a 100 MHz clock for the AXI4 and AXI4-Stream interfaces.

The DUT and other modules of the example design are kept under reset until MMCME2 is locked.

Register configuration module : This module configures the DUT registers as mentioned in the programming sequence in Programming Sequence . This module is an AXI Traffic Generator module that is configured to program the registers. For more information, refer to the AXI Traffic Generator LogiCORE IP (PG125) [Ref 7] .

Read path generator: This uses an AXI block RAM which is filled (with a fixed amount of transfers) after MMCME2 is locked. MM2S channel reads this AXI block RAM and transfers data to the AXI4-Stream interface.

Read path checker: This module checks the data transferred on the MM2S AXI4-Stream interface.

Read path CTRL checker : This module checks the data transferred on the MM2S AXI4-Stream Control Interface.

Write path generator : When the Write (S2MM) channel is configured, this module drives the transactions (with a fixed amount of transfers) on the S2MM AXI4-Stream interface.

Write path STS generator : This module generates the S2MM STS data stream.

Write path checker : This module checks the data received on the AXI4 interface. Data received on the AXI4 interface is also written into another AXI block RAM.

The test starts soon after the MMCME2 is locked. The Done pin is asserted High after all the transactions are completed. Similarly the Status pin is asserted High, when the data integrity check is successful. These two pins can be connected to LEDs to know the status of the test.