After following the steps described in Design Flow Steps, implement the example design as follows:
- Right-click the core in the Hierarchy window, and select Open IP Example Design.
- A new window pops up, asking you to specify a directory for the example design.
Select a new directory, or keep the default directory.
A new project is automatically created in the selected directory and opened in a new Vivado IDE window.
- In the Flow Navigator (left-side pane), click Run Implementation ,and follow the directions.
The following tables describe the files in the example design, simulation, and constraints directories.
In the current project directory, a new project with the name
<component_name>_example is created and the files are
delivered in that directory. This directory and its subdirectories contain all the
source files that are required to create the AXI DMA controller example design.
The following table shows the files that are part of the example design.
| Name | Description |
|---|---|
| <component_name>_exdes.vhd | Top-level HDL file for the example design. |
| axi_lite_sm.vhd |
Register configuration file for example design. (This file is not used by default. You can update the <component_name>_exdes.vhd to use in place of AXI Traffic Generator). |
| clock_gen.vhd | Clock generation module for example design. |
| axi4_write_master.vhd | Read path data generator module for example design. |
| axis_data_read.vhd | Read path data checker module for example design. |
| axis_write_master.vhd | Write path data generator module for example design. |
| axi_s2mm_read.vhd | Write path data checker module for example design. |
| axis_ctrl_read.vhd | MM2SCTRL data checker |
| axis_sts_master.vhd | S2MM STS data generator |
| sg_mif.coe | COE file used by block memory to store BDs |
The following table shows the test bench file that can be used to run the simulation.
| Name | Description |
|---|---|
| <component_name>_exdes_tb.vhd | Test Bench for the example design |
The following table shows the XDC file that is needed to implement the example design.
| Name | Description |
|---|---|
| <component_name>_exdes.xdc | Top level constraints file for the example design. |
The XDC delivered with the example design has all the I/O pins configured for KC705 board. These constraints are commented by default. Uncomment them before proceeding with implementation for the KC705 board.