S2MM_CURDESC_MSB (S2MM DMA Current Descriptor Pointer Register – Offset 3Ch) - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

This register provides the upper 32 bits of Current Descriptor Pointer for the Stream to Memory Map DMA Scatter Gather Descriptor Management. This is used only when DMA is configured for address space greater than 32 bits.

Figure 1. S2MM CURDESC_MSB Register

Table 1. S2MM CURDESC_MSB Register Details
Bits Field Name Default Value Access Type Description
31 to 0 Current Descriptor Pointer zeros R/W

(RO)

Indicates the pointer of the current Buffer Descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1,CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.

When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.

On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.

Note: The register can only be written to by the CPU when the DMA Engine is halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO).