Stream Data Width - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

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7.1 English

Data width in bits of the AXI S2MM AXI4-Stream Data bus. This value must be equal or less than the Memory Map Data Width. Valid values are 8, 16, 32, 64, 128, 512 and, 1,024.

TIP: When IP is used in the Vivado IP integrator, this parameter is automatically set based on the connection made to the s_axis_s2mm interface.