Resets - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

The axi_resetn signal needs to be asserted a minimum of 16 of the slowest clock cycles and needs to be synchronized to s_axi_lite_aclk.