Hardware Debug - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The AMD Vivado™ debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems.

Some of the common problems encountered and possible solutions follow.

  • You have programmed your BD ring but nothing seems to work. Register programming sequence has to be followed to start the DMA. See Programming Sequence and Descriptor Management.
  • Internal Error/Error bits set in the Status register
    • Internal error will be set when BTT specified in the descriptor is 0.
    • SG internal error will be set if the fetched BD is a completed BD.
    • Other error bits like Decode Error or Slave Error would also be set based on the response from Interconnect or Slave.
  • You are reading data from a location, but the data does not seem to be in order.

    Verify if the start address location is aligned or unaligned. If it is not aligned, ensure that the DRE is enabled while configuring DMA.

Also see the Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.