Field Descriptions - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English
Figure 1. Customize IP Options

Figure 2. IP Integrator

Component Name
The base name of the output files generated for the core. Names must begin with a letter and can be composed of any of the following characters: a to z, 0 to 9, and "_".
Enable Asynchronous Clocks
This setting provides the ability to operate the MM2S interface m_axi_mm2s_aclk, S2MM interface m_axi_s2mm_aclk, AXI4-Lite control interface s_axi_lite_aclk, and the Scatter Gather Interface m_axi_sg_aclk asynchronously from each other. When Asynchronous Clocks are enabled, the frequency of s_axi_lite_aclk must be less than or equal to m_axi_sg_aclk. Likewise m_axi_sg_aclk must be less than or equal to the slower of m_axi_mm2s_aclk and m_axi_s2mm_aclk. When in synchronous mode, all clocks inputs should be connected to the same clock signal. This parameter is automatically set in the Vivado IP integrator based on the clocks connected to axi_dma.
Tip: This parameter is automatically set when the IP is used in the Vivado IP integrator.
Enable Scatter Gather Engine
Checking this option enables Scatter Gather Mode operation and includes the Scatter Gather Engine in AXI DMA. Unchecking this option enables Direct Register Mode operation, excluding the Scatter Gather Engine from AXI DMA. Disabling the Scatter Gather Engine causes all output ports for the Scatter/Gather engine to be tied to zero and all of the input ports to be left open.
Enable Micro DMA
Checking this option generates a highly optimized DMA which is low on resource count. This setting can be used for applications that transfer a very small amount of data. Program the DMA based on the configuration selected. For example, the maximum bytes that can be transferred per transaction or per BD cannot exceed the following:

MMapData_width * Burst_length/8.

Similarly, the 4K boundary check is also not implemented in this mode restricting addressing to burst boundaries.

Width of Buffer Length Register
This integer value specifies the number of valid bits used for the Control field buffer length and Status field bytes transferred in the Scatter/Gather descriptors. It also specifies the number of valid bits in the RX Length of the Status Stream App4 field when Use Rxlength is enabled. For Direct Register Mode, it specifies the number of valid bits in the MM2S_LENGTH and S2MM_LENGTH registers. The length width directly correlates to the number of bytes being specified in a Scatter/Gather descriptor or number of bytes being specified in App4.RxLength, MM2S_LENGTH, or S2MM_LENGTH. The number of bytes is equal to 2LengthWidth -1. So a Length Width of 26 gives a byte count of 67,108,863 bytes. This value should be set to 23 for Multichannel mode.
Address Width (32 - 64)
Specify the width of the Address Space. It can be any value between 32 and 64.
Enable MultiChannel DMA
Note: The MultiChannel feature will be discontinued soon. For information on MultiChannel, see the AXI Multichannel Direct Memory Access LogiCORE IP Product Guide (PG288).

Checking this option enables multichannel capability of DMA and lets you choose the number of channels for both MM2S and S2MM channels. See Multichannel DMA Support for details.

Enable Control/Status Stream
Checking this option enables the AXI4 Control and Status Streams. The AXI4 Control stream allows user application metadata associated with the MM2S channel to be transmitted to a target IP. User application fields 0 through 4 of an MM2S Scatter/Gather Start Of Frame (SOF) descriptor Transmit Start Of Frame (TXSOF =1) are transmitted on the m_axis_mm2s_cntrl stream interface along with an associated packet being transmitted on the m_axis_mm2s stream interface. The AXI4 Status stream allows user application metadata associated with the S2MM channel to be received from a target IP. The received status packet populates user application fields 0 to 4 of an S2MM Scatter / Gather End of Frame (EOF) descriptor. That is the descriptor associated with the end of packet. This condition is indicated by a Receive End of Frame (RXEOF = 1) in the status word of the updated descriptor.
Enable Read Channel Options
The following options affect only the MM2S Channel of the AXI Direct Memory Access (DMA) core.
Enable Channel
This option enables or disables the MM2S Channel. Enabling the MM2S Channel allows read transfers from memory to AXI4-Stream to occur. Disabling the MM2S Channel excludes the logic from the AXI DMA core. Outputs for MM2S channel are tied to zero and inputs are ignored by AXI DMA.
Number of Channels
This option specifies the number of channels from 1 to 16.
Memory Map Data Width
Data width in bits of the AXI MM2S Memory Map Read data bus. Valid values are 32, 64, 128,256, 512, and, 1,024.
Stream Data Width
Data width in bits of the AXI MM2S AXI4-Stream Data bus. This value must be equal or less than the Memory Map Data Width. Valid values are 8, 16, 32, 64, 128, 512, and, 1,024.
Max Burst Size
Burst partition granularity setting. This setting specifies the maximum size of the burst cycles on the AXI4 side of MM2S. Valid values are 2, 4, 8,16, 32, 64, 128, and 256.
Allow Unaligned Transfers
Enables or disables the MM2S Data Realignment Engine (DRE). When checked, the DRE is enabled and allows data realignment to the byte (8 bits) level on the MM2S Memory Map datapath. For the MM2S channel, data is read from memory. If the DRE is enabled, data reads can start from any Buffer Address byte offset, and the read data is aligned such that the first byte read is the first valid byte out on the AXI4-Stream.
Note: If DRE is disabled for the respective channel, unaligned Buffer, Source, or Destination Addresses are not supported. Having an unaligned address with DRE disabled produces undefined results. DRE Support is only available for the AXI4-Stream data width setting of 512-bits and under.
Enable Write Channel Options
These options affect only the S2MM Channel of the AXI DMA core.
Enable Channel
This setting enables or disables the S2MM Channel. Enabling the S2MM Channel allows write transfers from AXI4-Stream to memory to occur. Disabling the S2MM Channel excludes the logic from the AXI DMA core. Outputs for S2MM channel are tied to zero and inputs are ignored by AXI DMA.
Number of Channels
This option enables you to choose a number of channels from 1 to 16.
Memory Map Data Width
Data width in bits of the AXI S2MM Memory Map Write data bus. Valid values are 32, 64, 128, 256, 512 and, 1,024.
Tip: In the Vivado IP integrator, this parameter is automatically set based on the data width of the Streaming Interface. Update this parameter by changing the switch to 'Manual'.
Stream Data Width
Data width in bits of the AXI S2MM AXI4-Stream Data bus. This value must be equal or less than the Memory Map Data Width. Valid values are 8, 16, 32, 64, 128, 512 and, 1,024.
Tip: When IP is used in the Vivado IP integrator, this parameter is automatically set based on the connection made to the s_axis_s2mm interface.
Max Burst Size
This setting specifies the maximum size of the burst cycles on the AXI4 side of the S2MM channel. In other words, this setting specifies the granularity of burst mapping. Valid values are 2, 4, 8, 16, 32, 64, 128, and 256.
Allow Unaligned Transfers
Enables or disables the S2MM Data Realignment Engine (DRE). When checked, the DRE is enabled and allows data realignment to the byte (8 bits) level on the S2MM Memory Map datapath. For the S2MM channel, data is written to memory. If the DRE is enabled, data writes can start from any Buffer Address byte offset, and the write data is aligned such that the first valid byte received on S2MM AXI4-Stream is written to the specified unaligned address offset.
Note: If DRE is disabled for the respective channel, unaligned Buffer, Source, or Destination Addresses are not supported. Having an unaligned address with DRE disabled produces undefined results. DRE Support is only available for AXI4-Stream data width setting of 512-bits and under.
Use RxLength In Status Stream
If the Control/Status Stream is enabled, checking this allows AXI DMA to use a receive length field that is supplied by the S2MM target IP in the App4 field of the status packet. This gives AXI DMA a pre-determined receive byte count, allowing AXI DMA to command the exact number of bytes to be transferred.

This option provides for a higher bandwidth solution for systems needing greater throughput. In this configuration, the S2MM target IP can supply all data bytes specified in the receive length field of status packet APP4.

Enable Single AXI4 Data Interface
This option is only applicable when used in the Vivado IP integrator. You can use this option to combine two AXI4 interfaces (MM2S and S2MM) into a single interface. This option does not affect the resource or performance.