Clocking - 7.1 English

There are four clock inputs:

• m_axi_mm2s_aclk for MM2S interface
• m_axi_s2mm_aclk for S2MM interface
• s_axi_lite_aclk for AXI4-Lite control interface
• m_axi_sg_clk for Scatter Gather Interface

AXI DMA provides two clocking modes of operation: asynchronous and synchronous. Setting Enable Asynchronous Clocks enables asynchronous mode and creates four clock domains. This allows high-performance users to run the primary datapaths at a higher clock rate than the DMA control (for example, AXI4-Lite interface, SG Engine, DMA Controller) helping in FPGA placement and timing.

In synchronous mode, all logic runs in a single clock domain. m_axi_sg_aclk, m_axi_mm2s_aclk, and m_axi_s2mm_aclk must be tied to the same source, the s_axi_lite_aclk can be connected to a slower clock. In asynchronous mode, clocks can be run asynchronously, however s_axi_lite_aclk must be less than or equal to m_axi_sg_aclk and m_axi_sg_aclk must be less than or equal to the slower of m_axi_mm2s_aclk or m_axi_s2mm_aclk.

The relationship between signal sets and their corresponding clocks in asynchronous mode is shown in the following table.