This register provides the upper 32 bits of Tail Descriptor Pointer for the Stream to Memory Map DMA Scatter Gather Descriptor Management. This is used when DMA is configured for address space greater than 32.
| Bits | Field Name | Default Value | Access Type | Description |
|---|---|---|---|---|
| 31 to 0 | Tail Descriptor Pointer | zeros | R/W | Indicates the pause pointer in a descriptor chain. The AXI DMA SG
Engine pauses descriptor fetching after completing operations on the
descriptor whose current descriptor pointer matches the tail
descriptor pointer. When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR_MSB register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, then writing to TAILDESC_PTR has no effect except to reposition the pause point. If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted =1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point. Note: The software must not move the Tail
Pointer to a location that has not been updated. The software
processes and reallocates all completed descriptors (Cmplted =
1), clears the completed bits and then moves the tail pointer.
The software must move the pointer to the last descriptor it
updated.
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