Register Space - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

The AXI DMA core register space for Scatter/Gather Mode is shown in Table 1. The AXI DMA core register space for Direct Register mode is shown in Table 1. The AXI DMA registers are memory-mapped into non-cacheable memory space. This memory space must be aligned on an AXI word (32-bit) boundary.

Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.