S2MM_DA_MSB (S2MM DMA Destination Address Register

S2MM_DA_MSB (S2MM DMA Destination Address Register – Offset 4Ch) - 7.1 English

AXI DMA LogiCORE IP Product Guide (PG021)

Document ID

PG021

Release Date

2024-06-20

Version

7.1 English

This register provides the upper 32 bits of Destination Address for writing to system memory for the Stream to Memory Map to DMA transfer. This is used only when DMA is configured for address space greater than 32.

Figure 1. S2MM_DA_MSB Register

Table 1. S2MM_DA_MSB Register Details
Bits	Field Name	Default Value	Access Type	Description
31 to 0	Destination Address	zeros	R/W	Indicates the MSB 32 bits of the destination address the AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel. Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.