Cyclic DMA Mode - 7.1 English

AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

Document ID
PG021
Release Date
2024-06-20
Version
7.1 English

AXI DMA can be run in cyclic mode by making certain changes to the Buffer Descriptor (BD) chain setup. In cyclic mode, DMA fetches and processes the same BDs without interruption. The DMA continues to fetch and process until it is stopped or reset. To enable cyclic operation, the BD chain should be set up as shown in the following figure.

Figure 1. BD Chain

In this setup the Tail BD points back to the first BD. The Tail Descriptor register does not serve any purpose and is used only to trigger the DMA engine. Follow the same programming sequences as mentioned in Scatter/Gather Mode. Ensure that the cyclic bit in the control register is set.

Program the Tail Descriptor register with some value which is not a part of the BD chain. Say for example, 0x50.

After the Tail Descriptor register is programmed, the DMA starts fetching and processing the BDs (which are set up in a ring fashion) until the DMA is stopped or reset.