Vivado Isolation Verifier (VIV) Checks 5 and 6

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

After implementation completes (placement and routing) without any errors, VIV is run again on the implemented design to validate that the required isolation is built into the design.

To run these DRCs, open the Report DRC window in the Reports drop-down menu, and select Implementation under Isolation, as shown in the following figure.

Figure 1. Report DRC Window

The result is displayed in the DRC window as shown in the following figure.

Figure 2. DRC Final Report

Ensure there are no errors in the DRC report.