For clarity, an example single-chip 2 channel functional safety design is used throughout this application note to describe the design details and tool flow. The following figure shows the floorplan for the lab design as implemented in an XCZU5CG-SFVC784-1-e device. It consists of five isolated regions. In addition, this design has been implemented with AMD Vivado™ Design Suite 2018.3, verified by the Vivado Isolation Verifier (VIV) 2.0, and provided to the designer as a reference.
Figure 1. IDF Design Floorplan
Access the isolation design for this application note from Isolation Design Example for Zynq Ultrascale+ MPSoC Application Note (XAPP1336).