Fence Around Processor Subsystem for Zynq UltraScale+ Devices

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)
Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

In Zynq UltraScale+ devices, there is a PSS Programmable Unit. This PU consists of the PSS_ALTO Tile, Interconnects, and a column of CLEs as high as the PSS tile. The following figure shows the PSS PU:

Figure 1. PU of PSS Alto Tile for Zynq UltraScale+ Device

The PSS PU cannot be a fence because of its fixed placement on the device. Additionally, it is not applicable as a fence because it does not sit between different logic tiles. But to isolate the PS logic from the rest, it does need a fence towards the right side of the PU – after the CLEs tiles of the PU and around the top right corner. The following figure shows how the fence can be drawn around the PSS PU.

Figure 2. How to Draw a Fence Around PSS PU

As shown in these following figures, no fence is needed towards the top of the PU. This is because there are no interconnects or connection for the top part of the PU with the rest of FPGA resources.

The following figure shows a zoomed in part for the regions where the fence is needed.

Figure 3. Zoomed in Image for Top-Right Part of the PSS PU

So, to isolate the PSS isolated Pblock (shown here in green color) with another adjacent isolated Pblock (shown here in blue color), you will need one column PU fence towards the right of the PSS PU, from top to bottom. In Figure 20: PU of PSS Alto tile for Zynq UltraScale+ Device, CLB PUs (the next available PU after the PSS PU) has been used as fence starting from the top of the PSS PU to the bottom (entire right side), of the PSS PU. The previous figure shows a zoomed in part of the same. Additionally, a fence comprising of 3 PUs is needed towards the top right to account for adjacency violation between the PSS Pblock (green) and the adjacent Pblock (blue). One PU fence is directly on top of the CLEs of the PSS PU. The other two PU fences are on the left and right sides. In the previous figure, the middle fence is made of a CLB PU, the left of it is a DSP PU, and the right of it is a CLB PU.

Note: The above screen captures are just for reference. The actual PUs for the fences might differ from part to part, e.g., instead of the DSP PU, the top left fence can be a CLB PU. However, you need to ensure that there is fence towards the whole right columns, as well as top right corner of the PSS PU (if used as part of isolation design). In smaller Zynq UltraScale+ devices there might not be any user tiles on top of the PSS PU, the whole left side of the part is the PSS PU. In that case, you may need a fence only towards the right column of the PSS PU (and not the top corner).