Drawing Pblocks Using Vivado GUI

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

Floorplanning is accomplished by using Pblocks. Drawing Pblocks is a multi-step process which is outlined here. This is the recommended process, but not the only method. See Drawing Pblocks Using Tcl Commands.

On a synthesized design:

  1. In the NETLIST window, right-click a module to be isolated. For this example, select a wrapper entry under design_1_i.
  2. Select Floorplanning > Draw Pblock as shown in the following figure.

  3. In the Device window, draw a rectangle that defines the initial Pblock as shown in the following figure.

    Once a Pblock is created, the Statistics window in Pblock Properties is updated, which outlines the percentage the Pblock resources that satisfies the synthesized requirements of the isolated region hierarchy as shown in the following figure.

  4. To add more resources to a Pblock, in the Device window, select the Pblock to highlight the region.
  5. Right-click the highlighted region, and select Add Pblock Rectangle. As you grow the size of the Pblock, the Statistics window will update showing added resources. Pblocks can be any shape.
  6. To delete the Pblock completely, in the Window drop down menu under Physical Constraints, right-click the Pblock entry, and click Delete as shown in the following figure.

    When drawing Pblocks, you will see shaded resources that show you which resources are included in the Pblock and which are not. All resources not in a Pblock (non-shaded) are fences. In the following figure, the red shaded resources are allocated to one Pblock, the green shaded resources are allocated to a second Pblock, and the blue shaded resources are allocated to a third Pblock. The regions outlines are only guidance artifacts from creating the Pblock and do not define resources. All non-shaded resources are fences, which means those resources are not being used.



    Pblocks can be any shape and size as shown in the following figure. This design enables green, red, and blue Pblocks to easily route to each other. The orange Pblock has all of the top level logic, and the yellow Pblock routes the orange Pblock.



  7. To complete the design and make sure your Pblock includes the required I/O Bank, assign pins. In this example, the orange Pblock contains the design I/Os.
    In the drop-down menu, select IO Ports to display the I/O Ports window.
    Note: In the following figure, the target I/O block is part of the orange Pblock. Ensure each Pin Assignment is fixed and has the correct I/O standard; otherwise, the final design rule check (DRCs) ran under Generate Bitstream will fail.