One of the most difficult concepts in IDF is the relationship between the logical ownership and the physical ownership of a user design.
Logical Ownership refers to the actual Hardware Description Language (HDL) of the design. Physical Ownership refers to where that design resides in an FPGA, i.e., the actual placement of the HDL logics in the FPGA fabric. The mapping from the logical ownership to the physical ownership happens when a Pblock is created and a logical instance is assigned to it. This binding of a logical instance or a portion of hierarchy, to a physical location in the device, is the foundation of the Isolation Design Flow. This is achieved with the following commands:
create_pblock <Pblock_name>
add_cells_to_pblock [get_pblocks <Pblock_name>] [get_cells -quiet [list */<isolated_module_name>]]
After the Pblock has been created and logic has been assigned to it, the Pblock must be defined (floorplanned) to add the necessary resources as discussed in Floorplanning. Note that any FPGA physical component - PU or routing resource that is not ranged / included in the Pblock definition cannot be used by the logic (module) assigned to that.
The following figure shows the logical ownership of four isolated modules – A, B, C, and D and the global clock.
The following figure shows the physical ownership for the four isolated modules of the previous figure. The logical modules have been assigned Pblocks in the FPGA using Vivado tools with a valid fence between them.
