It needs to be ensured that no global logic is logically contained in modules that are to be isolated. This is due to the UltraScale+ architecture that prohibits the isolation of such components due to their large scope. To aid non-isolation of global logic, Vivado tools allow you to keep your global logic as is (without HDL modification) by giving you the option to target said logic with an attribute that exempts it from isolation. This is a key feature in Vivado tools, because there are many IPs that have global logic embedded in them (BUFGs and MMCMs or Debug Hubs for example). In such cases, you identify them with a search and add the HD.ISOLATED_EXEMPT attribute to them.
An example of exempting Global Clocks from Isolation:
set_property HD.ISOLATED_EXEMPT true [get_cells -hierarchical -filter
{PRIMITIVE_TYPE =~ CLK.BUFFER.*}]These filter statements are very generic (wild cards). More specific operations can be performed if there are some clocks that need exemption and some that do not.
Isolating Clock Nets needs special handling. There are two types of clock nets from IDF point of view:
- Global Clock Net
- A Clock net which is crossing the Isolated Module boundary. That means a clock net which has loads in more than one isolated module.
- Local Clock Net
- Clock net which is contained within an Isolated module. That means a clock net which has loads in one Isolated module.