This application note describes how to implement security- or safety-critical designs using the AMD Isolation Design Flow (IDF) with the AMD Vivado™ Design Suite. Design applications include information assurance (single-chip cryptography), avionics, automotive, and industrial applications. This document explains how to address the following objectives:
- Implement isolated functions in an AMD Zynq™ UltraScale+™ MPSoC or an UltraScale+ FPGA
- Verify the isolation using the AMD Vivado Isolation Verifier (VIV)
You can purchase the Security Monitor IP core Product Brief developed by AMD to add additional security to your design. For more information, contact your local AMD representative to access these documents.
This application note specifically covers Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs using Vivado Design Suite 2018.3, and builds on earlier IDF concepts.
An example design is provided in the Isolation Design Example for Zynq Ultrascale+ MPSoC Application Note (XAPP1336). For more information, see Isolation Design Example.