Some initial architecting and floorplanning of the FPGA/SoC, coupled with a list of constraints, is all that is required to achieve isolation of specific modules within a single FPGA or SoC. It is important to note that any logic that is not isolated is, by definition, unconstrained logic and can be placed or routed by the tools in any isolated Pblock. Due to this, it is highly recommended that only global logic remains unconstrained, and global logic should be minimized. The following example shows the constraints generated by the tools when an isolated module is floorplanned into a specific region of the device using Pblocks and Vivado GUI as discussed in the Floorplanning section.
As an example, isolation of the Pblock_MAILBOX_WRAPPER module
of XAPP1336 is achieved by the following Tcl statements (commands):
create_pblock Pblock_MAILBOX_WRAPPER
resize_pblock pblock_MAILBOX_WRAPPER -add {SLICE_X2Y181:SLICE_X9Y239 BUFCE_LEAF_X16Y12:BUFCE_LEAF_X55Y15 BUFCE_ROW_FSR_X3Y3:BUFCE_ROW_FSR_X11Y3 DSP48E2_X0Y74:DSP48E2_X2Y95}
add_cells_to_pblock pblock_MAILBOX_WRAPPER [get_cells [list design_1_i/MAILBOX_WRAPPER]] -clear_locs