Isolation Properties

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

The Vivado tool uses two specific properties to create an isolated design: HD.ISOLATED and HD.ISOLATED_EXEMPT.

The Vivado tool enables isolation of a specific function by the application of the HD.ISOLATED property on the function. This property can be set either in the XDC file or the Vivado Integrated Design Environment (IDE).

The Tcl command is:

set_property HD.ISOLATED true [get_cells <function_hierarchical_path>/<function_instance_name>]

or

set_property HD.ISOLATED 1 [get_cells <function_hierarchical_path>/<function_instance_name>]

You can also set the property in the Vivado GUI. See Adding Property HD.ISOLATED under Elaboration for setting the property via Vivado IDE.

By default, when HD.ISOLATED is enabled on a function/module, all components and routing that belong to that module are isolated. This means that unless it is communicating with another isolated module, all routing is contained within that module. This also means that all components of that module are placed in its corresponding isolated Pblock.

Note: You do not explicitly add any isolation property to a Pblock. When an isolated module having the property HD.ISOLATED set is mapped to a Pblock during the floorplanning stage, that Pblock becomes an isolated Pblock. For further details, see Mapping the Logical Ownership to the Physical Ownership.

When the HD.ISOLATED property is set on a module, global logic instantiated within that isolated module cannot be routed globally because the module has been isolated. But, Vivado IDF allows you to instantiate global logic at any level. To support this and enable routing of the global logic, the property HD.ISOLATED_EXEMPT should be set on the global instances to override the default isolation behavior. By setting this property on the global logic instance, Vivado routes and treats it as global logic instead of isolated logic.

The format to exempt a global logic instance from isolation is:

set_property HD.ISOLATED_EXEMPT true [get_cells <function_hierarchical_path>/
<function_instance_name>]

or

set_property HD.ISOLATED_EXEMPT 1 [get_cells <function_hierarchical_path>/
<function_instance_name>]

See Guidelines for Controlling Global Clocking Logic for more information regarding the HD.ISOLATED_EXEMPT property, including an example of setting HD.ISOLATED_EXEMPT on all global logic in the design.

Note: Only global logic can be at the top of an isolated design, but it can also be instantiated in an isolated hierarchy if the HD.ISOLATED_EXEMPT property is used. By setting this property on global logic, the Vivado tool effectively treats them as top level logic.
Important: Every physical component in the FPGA including IOBs needed by an isolated module, must be owned by its corresponding isolated Pblock. The designer needs to create Pblocks in such a way that it has all the resources needed by the corresponding isolated module. This implies that IOBs needed by an isolated module must also be included in the corresponding isolated Pblock. For details on floorplanning, see Floorplanning.