Elaboration

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

In Isolation Design Flow (IDF), the HD.ISOLATED property is added and enabled for each user-created wrappers that need to be isolated from each other. All other modules that do not require isolation do not get this property added. Such modules will get optimized to top level and have no place and route restrictions beyond keeping the fence intact. At this point in the design flow, this property is added on each wrapper, so synthesis knows which hierarchy is isolated, preventing optimization across isolation boundaries.

Figure 1. Adding Property HD.ISOLATED

Figure 2. Enabling HD.ISOLATED