HDIO versus HPIO PUs

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID

XAPP1335

Release Date

2023-05-15

Revision

2.2 English

HDIO

As listed in Table 1, HDIO has the following fence rule:

Minimum fence width (vertical fence) is ½ HDIO
Minimum fence height (horizontal fence) is ½ HDIO PU

HDIO PU is a special PU where ½ of it can be used as fence. That also means half of it can be included in a Pblock.

HPIO

As listed in Table 1, HPIO has the following fence rule:

Minimum fence width (vertical fence) is 1 HPIO PU
Minimum fence height (horizontal fence) is 1 HPIO PU

A HPIO tile consists of 4 XiPHYs and a CMT tile along with the IOBs. And the HPIO PU, in addition to the HPIO tile components consists of CLEs sharing the interconnects with HPIO tile. This whole PU must be used as fence whenever isolation is needed. The following figure shows the HPIO PU with all the component tiles.

Figure 1. HPIO PU with All the Sub-Components

Note: Individual tiles of HPIO such as XiPHY and CMT cannot be used as fence, whenever needed the entire HPIO PU must be used for fence.

As with any other PUs, for IDF design, two HPIO PUs belonging to two different isolated Pblocks cannot be adjacent to each other. They will need a least one unprogrammed HPIO PU (not included in any Pblock) as fence between them. The following figure shows a valid fence between two HPIOs belonging to two different isolated Pblocks.

Figure 2. Green and Blue Isolated Pblocks Separated by an HPIO PU Fence

Note: While it is understood that the user will incur a huge penalty while using HPIO PU as fence by not being able to use 52 IO pins, this is needed to achieve isolation as the CMT tile of HPIO spans the complete PU and it shares interconnect with all the tiles in the HPIO PU.