There are some configuration blocks in the FPGA that looks like gaps but are not a fence. The following figure highlights such a gap with a white rectangle. These blocks cannot be used as a fence. However, a valid block RAM PU fence has been shown with green rectangle.
Note: The following figure shows
the routing view in the Vivado IDE. AMD recommends always using the device view in the Vivado IDE to look at fences and create Pblocks while using the IDF. The
routing view is good for determining PUs, if needed.
Figure 1. Config Block Highlighted in White Rectangle Looks like a Fence,
but It Is Not
