Configuration Blocks Gap

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

There are some configuration blocks in the FPGA that looks like gaps but are not a fence. The following figure highlights such a gap with a white rectangle. These blocks cannot be used as a fence. However, a valid BRAM PU fence has been shown with green rectangle.

Note: The following figure shows the routing view in Vivado. It is highly recommended to always use device view in Vivado to look at fences and create Pblocks while using IDF. The routing view is good for determining PUs if needed.
Figure 1. Config Block Highlighted in White Rectangle Looks like a Fence, but It Is Not