Netlist

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

The driver of the clock net and all the loads of the clock net must be primitive cells under IDF module hierarchy (i.e., the parent module where the HD.ISOLATED property is set).

Figure 1. IDF Module