Resources to Add in an Isolated Pblock

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

It is generally advised to add all the available resources i.e. Programmable Units (PUs) within an isolated Pblock (except those that are needed for the fence), even if the logic tile/PU is not used in the design, because excluding them also excludes using their respective routing resources. Failure to do so, while not an error, might produce designs that are very difficult to route. This is true even for the I/O clock buffers.

However, in the Vivado tool, BUFGs and BUFHs must not be included in the isolated Pblocks unless you want the global clock isolated (not advisable unless the design warrants it to be isolated). All other components must be included.

Note: Resources that are not associated with a Pblock cannot be used even if it is needed by top level logic. Resources not assigned to any Pblock are invisible to placement and routing tools. If global clock in an IP is owned by any isolated module it needs to be exempted from isolation using HD.ISOLATION_EXEMPT property.