Developing a safe and secure single chip solution that contains multiple isolated functions in a single FPGA is made possible through AMD isolation technology. Special attributes, such as HD.ISOLATED and the features it enables, are necessary to provide controls to achieve the isolation needed to meet certifying agency requirements.
To better understand the details of the Isolation Design Flow (IDF), the designer needs to have a solid understanding of the hierarchical design flow, see Vivado Design Suite User Guide: Hierarchical Design (UG905). Many of the terms and processes in the partition flow are used in the IDF. Areas that are different supersede the partition design flow and are identified in this application note.