Constraint Check (VIV-Constraints)

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID

XAPP1335

Release Date

2023-05-15

Revision

2.2 English

VIV, on the floorplan, checks the following:

IDF_VIV2-1 – Provenance:

IDF_VIV2-1 is an advisory DRC documenting the circumstances of the run. It also validates that the design has at least two modules marked as isolated (using the HD.ISOLATED property). Nets driven by cells marked HD.ISOLATED_EXEMPT are exempt from inter-region isolation rules and are listed in the IDF_VIV2-1 output. This DRC also checks that the SNAPPING_MODE property of each Isolated Pblock is set to FINE_GRAINED.

IDF_VIV2-2 - I/O Bank Violation:

Pins from different isolation regions are not co-located in the same IOB bank.

Note: While VIV does fault such conditions, only specific security related applications require such bank isolation. Most applications allow sharing of IO banks. Bank sharing is dependent on the specific application and users need to take decision to allow bank sharing per use case basis.

IDF_VIV2-3 - Package Pin Violation:

Pins from different isolation groups are not physically adjacent, vertically or horizontally, at the die level.

Pins from different isolation groups are not physically adjacent at the package level. Adjacency is defined in eight compass directions: north, south, east, west, northeast, southeast, northwest, and southwest.

IDF_VIV2-4 - Floorplan Violation:

The Pblock constraints in the XDC file are defined by the user such that a minimum fence as listed in Table 1 exists between isolated Pblocks. This means Pblocks are drawn with valid fence between them.