Enable IDF+DFX Flow

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

A combined flow of IDF+DFX is enabled by default for all Zynq UltraScale+ MPSoC devices but the user need to set a param to enable the appropriate set of design rule checks for IDF+DFX. Prior to Vivado version 2021.1, these DRCs are disabled by default. The steps below demonstrate on how to enable them. But from Vivado version 2021.1 onwards the DRCs are gets enabled automatically when the tool detects HD.ISOLATED property is set to True in the Vivado design and no additional steps are needed. Users need to enable IDF and DFX separately as mentioned in the Isolation Design Flow of this document and in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909). Prior to Vivado version 2021.1, set the following parameter to enable IDF+DFX DRCs.

set_param hd.enableIDFDRC 1

This parameter information is not stored in the database so must be re-enabled in each Vivado session. The parameter is most easily set in your vivado_init.tcl. For more details on how to run VIV DRCs, refer to Vivado IDF Verifier (VIV) Checks 1,2,3, and 4 and Vivado Isolation Verifier (VIV) Checks 5 and 6 of this document.

Both the project mode and the non-project Tcl scripted mode are supported. The DFX flow for IP integrator, however, is still in early access. You can refer to the Isolation Design Flow of this document and Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) for flow requirements and details for topics such as:

  • The use of HD.ISOLATED and HD.RECONFIGURABLE to define the functionality of a given level of hierarchy
  • Fence creation guidelines and rules for IO and clocks for the isolation design flow
  • Logical decoupling and partial bitstream delivery for the dynamic function eXchange flow

Routing expansion in IDF+DFX flow works same as DFX flow. The reconfigurable partition in the combined IDF+DFX solution is subject to more stringent regulations given the isolated modules that surround it. These additional rules must be considered when floorplanning the reconfigurable partition, and when designing each RM that will be placed in that RP:

  • Expanded routing for RPs is enabled, but routing is contained per isolated module to follow IDF rules
  • No embedded clocks are allowed within an isolated module within any reconfigurable module
  • Each interface on the reconfigurable partition must connect to only one isolated module outside the RP*
Note: *Features planned for the future Vivado releases.

For this last item, the current requirement is that a trusted route starts in one IM and connects to only one other IM; no net splitting is supported. If a trusted route must go to more than one IM, the user must create additional drivers and ports that will each connect to a single IM. The following image shows one unsupported scenario in Vivado 2021.1 and prior versions.. A similar scenario of a driver in a static IM driving loads in multiple IMs, at least one of which is within an reconfigurable partition (RP), would also be unsupported.

Figure 1. Unsupported Connectivity That Requires Net Splitting

While net splitting is not currently supported by the tools, it can be done manually. The support for automatic net splitting will be added in future Vivado releases.

Figure 2. Workaround Using Replication of Drivers