Pblock Horizontal Edges

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

For UltraScale+ devices, HDIST nodes could straddle up to two adjacent clock regions horizontally. See RED HDIST Node displayed in the following figure. If a Pblock is fully clock-region aligned (as shown in green in the following figure), then the left end of the red HDIST node will fall into the fence region and causes the clock net does not honor routing exclusion requirement due to routing nodes notification to appear.

Figure 1. Isolated Pblock with HDIST Node Inside.

The solution is to adjust the Pblock left/right edge to contain the whole HDIST node horizontally.

Figure 2. Isolated Pblock With HDIST Node Inside