Second Configuration

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English
  • Link the complete design for second configuration using the top static route dcp and RM synth dcps. You may refer to Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947) for further details.
  • The static route dcp does not contain floorplanning information for nested IMs inside of the RP. It contains Pblock information for static IMs and PR region only.
  • If there is no change in the hierarchy and floorplan inside the PR from the previous configuration, then use the already saved XDC file and load the floorplan for nested IMs. If there is a change in the hierarchy or floorplan, then create new floorplanning by following IDF and IDF+DFX guidelines. Refer to the Drawing Pblocks Using Vivado GUI section for drawing Pblocks using the Vivado GUI.
  • Run VIV DRC checks 1, 2, 3, and 4. Refer to Vivado Isolation Verifier User Guide (UG1291) on how to select and run VIV DRCs. Do not run VIV implementation DRCs (check 5 and 6) at this point as the design is not implemented yet. Ensure there are no DRC warnings or error.
  • Save the Pblocks for nested IMs. You can use the script provided with Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947).
  • Implement the design by using the standard DFX implementation flow.
  • Run all VIV DRC checks on the implemented design. Ensure there are no warnings or errors.

You may similarly implement all the configurations. For pr_verify, bitstream generation, and for loading the FPGA, follow the standard DFX flow.

Figure 1. IDF+DFX Design Flow Steps Second Configuration