Before an isolated design can be implemented, a floorplanning strategy must be manually entered. This placement restriction uses Pblocks, which are drawn on the device in the Device window. For logic that is outside an isolated hierarchy (such as top level logic), this logic can be in any Pblock.
FPGA arrays are made up of multiple clock regions with columns of logic resources within each clock region. Each logic resource has a fixed height which are stacked one on top of another to make up a column as shown in the following figure. Pblocks span these regions, but if a resource, such as a PCI® block, which takes an entire clock region, is not enclosed by a single Pblock, it will not be included in the Pblock. Before creating each Pblock, map out where each Pblock will be located.
