Programmable Unit Size Examples

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

The smallest programmable unit (PU) is the CLB PU unit shown in the following figure. The CLB PU unit is 1/60th of a clock region high and two columns wide.

Figure 1. CLB PU

The next smallest programmable units are the DSP PU UNIT and the BRAM PU UNIT shown in the following figures.

Figure 2. DSP PU

Figure 3. BRAM PU

The URAM PU is shown in the following figure.

Figure 4. URAM PU

The tallest PUs are:

52 HPIO PU
One clock region high and two columns wide
4 Channel GTH PU
One clock region high and three columns wide
SYSMON PU
One clock region high and also three columns wide

Other one clock high PU units include PCIe® and CMAC.

Figure 5. HPIO PU

Figure 6. GTH QUAD PU

Figure 7. SYSMON PU

Figure 8. HDIO PU