A secure or safety-critical solution can be achieved while using FPGA design techniques and coding styles with only moderate modifications to the development flow. AMD Isolation Design Flow (IDF) development requires the designer to consider floorplanning much earlier in the design process to ensure that proper isolation is achieved in logic, routing, and I/O buffers (IOBs). In addition to early floorplanning, the development flow is based on hierarchy. Each function that is being isolated must be at its own level of hierarchy. Although this flow requires additional steps, the hierarchical approach has certain advantages.
There are a few unique design details that must be adhered to achieve an FPGA-based IDF solution. Carefully consider all aspects of the design details explained in subsequent sections of this application note. These considerations include:
- Keep each function that is being isolated at its own level of hierarchy.
- Keep top level or non-isolated logic to a minimum. It is strongly encouraged to have only global clocks and resets at this level.
- Use a fence to separate isolated functions.
- IOBs must be instantiated inside isolated modules for proper
isolation of the IOB. This can be achieved by manual user instantiation or
automatically by the tools.Note: Automatic logical inferencing by the tools is unique to the AMD Vivado™ Design Suite.
- On-chip communication between isolated functions is achieved through the use of trusted routing (Tools automatically choose trusted routes along coincident physical borders).