Drawing Pblocks Using Tcl Commands

When you draw Pblocks using the GUI as discussed above, the corresponding constraints gets saved to XDC files. In addition to using GUI, you can also use Tcl commands to create Pblocks by executing those commands in the Vivado Tcl Console or saving them in the XDC file. The following example uses one of the modules - MAILBOX_WRAPPER of XAPP1336 reference design to show how Tcl commands can be used as part of the XDC file to create an isolated Pblock.

Important: The discussion in this section of doing floorplanning using Tcl commands is an advanced topic. The same can be achieved by using the Vivado Design Suite GUI as explained in above section. This section can be used as reference if Pblocks need some fine adjustments or otherwise can be used for understanding how the tools work behind the hood. AMD highly recommends to use Vivado GUI for Floorplanning.

create_pblock creates a Pblock that allows adding the logic instances inside it as shown below:

create_pblock pblock_MAILBOX_WRAPPER

add_cells_to_pblock command is then used to assign the isolated module's logic elements / instances to the newly created Pblock as shown below:

add_cells_to_pblock Pblock_MAILBOX_WRAPPER [get_cells[list design_1_i/MAILBOX_WRAPPER]-clear_locs

Once isolated modules/cells are assigned to the Pblock, the isolated Pblock must be assigned to a specific range of logics/PUs in the FPGA. Isolated regions/Pblocks can be defined in terms of SLICEs, RAMB18s, RAMB36s, IOBs, ILOGICs, OLOGICs, IDELAYs, ODELAYs, PLLs, MMCME2s, IN_FIFOs, OUT_FIFOs, BUFGCTRLs, GTXs, DSP48s. Adding components (specified range of sites) to an isolated Pblock is done by using the Tcl command resize_pblock as shown below:

resize_pblock Pblock_MAILBOX_WRAPPER -add {SLICE_X2Y181:SLICE_X9Y239 BUFCE_LEAF_X16Y12:BUFCE_LEAF_X55Y15 BUFCE_ROW_FSR_X3Y3:BUFCE_ROW_FSR_X11Y3 DSP48E2_X0Y74:DSP48E2_X2Y95}

The generic format for the Tcl command for adding the ranges resize_pblock is:

resize_pblock -add {<comp name>_XaYb:<comp name>_XcYd

Where <comp name> = name of desired component, for example: SLICE, DSP48, and RAMB36, etc.

The component name can be identified by pointing at it in the Device view in the Vivado tool and reading it off the bottom right side of the screen. Coordinates can also be identified from the same location that the component name was identified.

a, b, c, d = Coordinates of the starting component and the ending components

A full listing of this syntax can be found in Vivado Design Suite Tcl Command Reference Guide (UG835).

Note: While creating Pblocks, ensure that the SNAPPING_MODE property is set to FINE_GRAINED. See Derived Range and Snapping Mode section.

Note: Even though the physical resources are being added using the sites, the end goal is to capture the Programmable Units in entirety and assign them to the Pblocks. See Pblocks and Programmable Units section.

Note: Nested Pblocks inside the isolated Pblocks is supported. Users can use nested Pblocks to meet timing closures. IDF supports only one level of nesting. Isolated Pblocks can have nested child Pblocks inside them, but the nested child Pblocks should not have child Pblocks.

Even if the design does not use DSP or block RAM PUs, they must be added to the isolated Pblock so that the routing resources contained by these PUs can be used. As a general rule, all available resources (except BUFGs and BUFHs i.e., global logics) should be assigned to the isolation Pblock unless there is specific need to exclude that resource. This is the default selection when generating the XDC file if you use the Vivado Design Suite GUI as discussed above to create isolated Pblocks. If you are not familiar using Tcl commands to create Pblocks and assign isolated modules to them, you are encouraged to use the Vivado Design Suite GUI tools for the same as explained in Drawing Pblocks for Floorplanning.